2.5-D / 3-D Status 2012

Philip Garrou
IEEE Fellow and Consultant
Microelectronic Consultants of NC

• Economic status
• Interposer status
• Processing
• Assembly
• Commercial status
• Infrastructure development

Break 2:10-2:30

Testing Three-Dimensional Stacked Integrated Circuits

Erik Jan Marinissen
Principal Scientist
IMEC

• Challenges and emerging solutions in 3-D-SIC testing
• Test Flows: pre-bond, mid-bond, post-bond, final test
• Test Contents: new structures, new defects, new patterns?
• Test Access: wafer probing and design-for-test

Break 3:40-4:00

Key Challenge Items for Wide IO Application and its Approach in Standard and Technologies to Solve Them

Minsuk Suh
Principal Enginee
SEMATECH/SK Hynix

• Wide I/O application
• Key challenge items
• Technology approaches
• Standards

The Evolution of 3-D ICs: Leaping Ahead of Moore's Law to Deliver a 6.8B TransistorDevice

Liam Madden
Corporate Vice President
Xilinx

• Evolution of 3-D ICs
• Comparative approaches by industry pioneers
• 28nm 3-D IC case study: world's highest capacity FPGA and first heterogeneous 3-D FPGA
• 3-D standards call to action Revolutionary Changes

Revolutionary Changes in Memory Technology and the Role of 3-D

J. Thomas Pawlowski,
Chief Technologist, Micron Fellow
Micron Technology

• Increasing importance of memory
• Scaling challenges
• The need for abstraction and demonstration thereof by HMC
• New system capabilities now reveal shortcomings elsewhere
• Future directions

Moore's Law, Semiconductor Economics, and Other Bellwethers of 3-D IC

Vinod Kariat
Vice President of R&D
Cadence Design Systems

• 3-D IC challenges: technology, ecosystem, and economics
• Semiconductor technology landscape and the emergence of the 'advanced node' gap
• Proof is in the pudding: 3-D IC proof points
• Solutions and methodologies
• Next steps

Technical Challenges and Progress in an Open Supply Chain Model

David McCann
Senior Director
GLOBALFOUNDRIES

• Test chip design for the supply chain
• Design tools
• Thinning impact on transistors
• Design for manufacturing
• Test

Perspectives on 3-D-integration; Trends, Drivers, and Possible Solutions

Carl Engblom
Director R&D
Ericsson

Break 10:30 – 11:00 am

TSV Package Integration: How Close Are We Really?

Ron Huemoeller
Senior Vice President, Advanced Product Platform Development
Amkor Technology

• Business case
• Infrastructure / Logistics
• Assembly readiness
• Product reliability
• Product release

Bumps on the Road to HVM of 3-D ICs

Jan Vardaman
President
TechSearch International

• Manufacturing and business issues push out adoption of 3-D TSV
• Challenges take time to resolve
• Companies seek alternatives for 3-D TSV
• Alternatives include interposers or 2.5-D: adoption has started
• PoP and other conventional stacked die solutions meet short-term needs

3-D IC & TSV Interconnects: Market Update & Infrastructure Readiness

Lionel Cadix
Market and Technology Analyst
Yole Développement

• The different flavors of 3-D integration
• Status of commercialization of 3-D ICs
• Supply chain challenges & infrastructure readiness for high volume manufacturing
• Challenges / bottlenecks ahead for HVM of 3-D ICs

Lunch 12:30 – 1:45 pm
Sponsored by Cadence Design Systems

Implementing 2.5-D and 3-D Devices

Robert Patti
CTO, Vice President of Design Engineering
Tezzaron Semiconductor

• Achieving fine 3-D pitch
• 3-D as a scaling solution
• 2.5-D and 3-D process updates
• New applications and technology approaches

Continued Adoption of Low Temperature Direct Bond Technology for High Volume 3-D Commercial Applications

Chris Sanders
CTO / Director Business Development
Ziptronix

• Homogeneous and heterogeneous direct bonding
• Submicron technology scaling
• Implementation options
• Wafer-to-wafer applications; image sensors and beyond
• Technology adoption status

3-D IC Technologies at CEA-Leti

Patrick Leduc
3-D IC Program Manager
CEA-Leti

• Interposer technology
• 3-D IC technology
• Evolution of Leti 3-D tool box
• An initiative to boost 3-D TSV adoption

The Development of TSV Technology in China

Daquan Yu
Professor
Chinese Academy of Sciences – Institute of Microelectronics

• Research status of TSV technology
• Progress of equipment development for TSV process
• Progress of materials development for TSV process
• EDA tool development for TSV integration

Break 3:45 – 4:15 pm

High Density 3-D IC Integration: Enabling Smart Imagers

John Lannon
Senior Research Engineer
RTI International

• Application examples
• Evolution of high density integration technology
• Remaining challenges

3-D Integration – Driving Heterogeneous Integration for System in Packages

M. Juergen Wolf
Fraunhofer IZM-ASSID

• 3-D wafer level approaches and alternatives
• TSV key processes and status
• 3-D Interconnect formation
• Silicon interposer
• Challenge and bottlenecks

A Versatile 2.5-D Heterogeneous Design and Integration Platform for "More-than-Moore" Technology

Dim-Lee Kwong
Executive Director
Institute of Microelectronics

• Design considerations for heterogeneous integration using TSI
• 2.5-D TSI technology platform
• The smart building blocks with I/O library
• Integrated PDK and EDA design flow
• The implementation—the MPW shuttle approach for TSI heterogeneous integration

Evening Reception 6:00 – 8:00 pm
Sponsored by EV Group

Design for 3-D Infrastructure: Quo Vadis

Riko Radojcic
Director
Qualcomm

• Tools, methodologies, models
• Lessons from memory on logic
• Status of 3-D standards
• Challenges beyond memory on logic

WIOMING: 3-D Technology, Design and Test Solutions for Ultra High Memory Bandwidth

Georg Kimmich
Technology Manager
ST Ericsson

Denis Dutoit
Research Engineer
CEA-Leti

• 3-D integration technology tool box
• WIOMING: performance, architecture, design methods, test solutions, manufacturing, and validation
• Outlook – 3-D technology for mobile applications

Manufacturing and Design Optimization for 2.5-D Integration

Arifur Rahman
Product Architect
Altera Corporation

• Overview and lessons learned
• Design consideration

3-D PathFinding Tools and Design Flow

Lisa McIlrath
President, CEO
R3Logicn

• Defining the problem
• Near term: 2.5-D interposer flow
• Constraint-driven floorplanning /placement
• 3-D cell libraries

Going 3-D by Evolution Rather than by Revolution: an EDA Supplier's Viewpoint

Steve Smith
Senior Director of Marketing, 3-D IC
Synopsys

• Why now?
• Scoping the challenges
• Technology trends and timeline
• 2.5-D and 3-D IC design flow
• Beyond IC; heading toward heterogeneous systems

Break 10:30 – 11:00 am

3-D-COSTAR: A Cost Model for 3-D Stacked ICs

Erik Jan Marinissen
Principal Scientist
IMEC

• Cost model assists in making trade-offs
• Design, manufacturing, test, packaging, and logistic costs
• Die-to-Die, Die-to-Wafer, and Wafer-to-Wafer stacking
• Pre-bond, mid-bond, post-bond, and final testing

Interconnect Testing of JEDEC Wide-I/O DRAM-on-Logic 3-D Die Stacks

Bassilios Petrakis
Cadence Design Systems

• JEDEC Wide-I/O DRAM standard includes boundary scan
• 3-D-DfT architecture extended to cover this
• Dedicated interconnect ATPG
• Successful case study on TSMC test chip

Fine-Pitch Micro-Bump Probing

Daniel Rishavy
Product Manager
Tokyo Electron America

• Avoiding the use of dedicated pre-bond probe pads
• Probing on fine-pitch micro-bumps
• Concerted alignment effort between probe card and probe station

Lunch 12:30 – 1:30 pm
Sponsored by SUSS MicroTec

From Unit Processes to Smart Process Integration

Thorsten Matthias
Director of Business Development
EV Group

• The paradigm shift in 3-D IC manufacturing
• Innovative process integration
• High yield through reduced manufacturing complexity

Wafer Level Interconnects for Packaging—Challenges and Solutions

Sesh Ramaswami
Managing Director
Applied Materials

• Roadmap
• Pillar/bump technologies – implications in 3-D stacks
• Industry progress and learnings in TSV for 3-D and 2.5-D integration
• CoO progress: 2009-2012
• A perspective on requirements for 20nm and beyond

Temporary Bonding and "PowerPoint Engineering"

Wilfried Bair
General Manager
SUSS MicroTec

• One process does not fit all
• Chemical demands
• Physical demands
• Throughput, quality, and cost
• Process extendability

Break 3:00 – 3:15 pm

Design and Testing Strategies for Modular 3-D Multiprocessor Systems Using Die-level Through Silicon Via Technology

Yusuf Leblebici
Professor
Swiss Federal Institute of Technology

• 3-D modular multi-core architectures
• Homogeneous and heterogeneous systems for 3-D integration
• Inter-layer communication schemes and network-on-chip solutions
• Die-level via-last copper TSV technology
• Testing strategies and experimental results

Scaling Hybrid-Integration of Silicon Photonics for Low Power Communications

John E. Cunningham
Consulting Hardware Engineer
Oracle Corporation

• DARPA UNIC
• SiPhotonics
• Macrochip
• Packaging and Integration

Closing Comments 4:15 pm