2012 Speakers

Carl Engblom
Director R&D
Ericsson

Vinod Kariat
Vice President R&D
Cadence Design Systems

Vinod Kariat is currently Fellow and vice president of R&D at Cadence Design Systems, where his responsibilities include custom layout automation and library characterization. Vinod has worked in various management and technical positions at Cadence since 2001, and has a broad background in design automation. Prior to joining Cadence, Vinod was co-founder and vice president of R&D at CadMOS Design Technologies, where he pioneered on-chip static noise analysis. Vinod has a PhD in computer engineering, is a senior member of IEEE, and holds 14 U.S. patents.

Liam Madden
Corporate Vice President
Xilinx, Inc.

Liam Madden is corporate vice president of FPGA Development and Silicon Technology at Xilinx. He has responsibility for FPGA design, Advanced Packaging (including 3-D Chip Stacking) and Foundry Technology. Madden joined Xilinx in 2008, bringing more than 25 years experience in design and technology leadership positions. He has contributed to a range of industry leading products, including: high performance and low power microprocessors (Alpha and StrongArm at DEC), embedded processors and IP (MIPS) and consumer devices (Xbox 360 at Microsoft). Prior to joining Xilinx, Mr. Madden was a Senior Fellow at AMD where he drove AMD's next generation chip integration methodology. He holds a BE degree from UCD and an M.Eng. degree from Cornell University.

David McCann
Senior Director
Global Foundries

David McCann is senior director for packaging R&D at Global Foundries in Malta, New York. In this role, he is responsible for Packaging R&D and back-end strategy and implementation. David started at Global Foundries in 2011.

Prior to Global Foundries, David worked at Amkor Technology for eleven years, most recently leading the BGA, Flip Chip and MEMS product groups. He was responsible for extensions of package technology, bump, applications, and business performance. He also led cross-functional teams in various areas including networking product strategy and mobile product development.

Prior to Amkor, David worked at Biotronik, GmbH in Portland, OR. Biotronik is a developer and manufacturer of implanted medical devices including defibrillators and pacemakers. He held various roles in product development, process development, and production. David has supported the Electronic Component and Technology Conference for more than 10 years. He was general chair in 2012.

David received his master's in engineering management from the Santa Clara University in 1985 and a BS in ceramic engineering from the University of Illinois in 1981.

J. Thomas Pawlowski
Chief Technologist, Micron Fellow
Micron Technology

J. Thomas Pawlowski is a Micron Fellow and chief technologist in the DRAM Solution Group's Architecture Development Group. He is responsible for the technical aspects of innovative products, technologies, memory, and systems architectures. He has created numerous ground-breaking memory architectures and concepts including Double Data Rate, Quad Data Rate, Double Address Rate, RLDRAM low-latency high-request rate memory, PSRAM, posted write concepts, High-Speed NAND concepts, hierarchical cache and cache control concepts, Phase Change memory concepts, logic and memory integration in 2-D, 2.5-D and 3-D, memory control concepts, and others to be disclosed in the future. Outside of the memory field, he has designed portions of planes, trains, automobiles, submarines, space station, computers, microprocessors, industrial controllers, analog and digital electronics, real-time and simulation software and operating systems. Thomas is also an entrepreneur, having started a successful loudspeaker company and is currently designing a revolutionary two-seat electric commuter car in his copious free time. He received a bachelor of applied science in electrical engineering from Waterloo in 1984 and has over 100 issued U.S. and international patents.

Philip Garrou
IEEE Fellow and Consultant
Microelectronic Consultants of NC

Dr. Philip Garrou consults in the areas of 3-D IC, thin film technology, IC packaging and interconnect and microelectronic materials for startups and fortune 500 companies. He received his BS degree in chemistry from North Carolina State University and his PhD in chemistry from Indiana University. He has authored or edited five microelectronic texts and has co-authored more than 100 technical publications and book chapters. .

Erik Jan Marinissen
Principal Scientist
IMEC

Erik Jan Marinissen is principal scientist at IMEC in Leuven, Belgium. Previously, he worked at NXP Semiconductors and Philips Research, both in Eindhoven, The Netherlands. Marinissen holds an MSc degree in computing science and a PDEng degree in software technology, both from Eindhoven University of Technology.

Erik’s research interests include all topics in the domain of test and debug of micro-electronics. He is co-author of over 170 journal and conference papers and co-inventor on nine granted U.S. and EP patent families. He is the recipient of the ITC 2008 and ITC 2010 Most Significant Paper Awards and Best Paper Awards at the Chrysler-Delco-Ford Automotive Electronics Reliability Workshop 1995 and the IEEE International Board Test Workshop 2002. He served as editor-in-chief of IEEE Std 1500 and founded and chairs the IEEE P1838 Working Group on standardization of a 3-D test access architecture. He is a founder of workshops on Diagnostic Services in Network-on-Chips, 3-D Integration, and Testing of Three-Dimensional Stacked Integrated Circuits. He serves on numerous conference committees, including ATS, DATE, ETS, ITC, and VTS, and on the editorial boards of IEEE Design & Test of Computers, IET Computers and Digital Techniques, and Springer’s Journal of Electronic Testing: Theory and Applications (JETTA). Erik is a Fellow of IEEE and Golden Core Member of Computer Society.

Minsuk Suh
Principal Enginee
SEMATECH/SK Hynix

Minsuk Suh received his master's doctoral degrees of material engineering and science at KAIST (Korea Advanced Institute of Science and Technology). In 2000, he joined SK hynix where he was in charge of advanced package technology development including WLP, Flip chip and TSV. He has been working at SEMATECH as SK Hynix assignee and bonding and assembly expert since 2011.

Minsuk is a member of package and interconnect committee of Semicon Korea technology symposium, and a member of package and interconnect committee of Korean conference on semiconductor. He also is a member of IMAPs and IEEE.

Wilfried Bair
General Manager
SUSS MicroTec

Wilfried Bair, SUSS MicroTec's vice president of strategic business development, is responsible for developing emerging market and business opportunities as well as strategic alliances for SUSS MicroTec. With many years of experience working in 3-D technologies and applications, he is focusing on SUSS' 3-D packaging and 3-D integration product portfolio. Additionally, Wilfried is the general manager of the based wafer bonder division of SUSS MicroTec.

Wilfried has over twenty years of management and business development experience in the semiconductor equipment and device industry throughout Europe, the U.S., and Asia. He holds an MS in manufacturing engineering as well as marketing and business administration from Johannes Kepler University, Linz, Austria.

Lionel Cadix
Market and Technology Analyst
Yole Développement

Lionel Cadix joined Yole Développement after the completion of several projects linked to the characterization and modeling of high density TSV and 3-DIC chip stacking in collaboration with CEA-LETI and STMicroelectronics during his PhD. He is author of several publications and eight patents in the field of 3-D integration.

John E. Cunningham
Consulting Hardware Engineer
Oracle Corporation

John Cunningham is a veteran research scientist with over 25 years of University, Bell Labs, Sun Labs of Sun Microsystems/Oracle, and start-up experience in the area of opto-electronic and semiconductor devices and packaging used within optical networks. Since joining Sun Microsystems / Oracle he has lead advanced packaging initiatives to develop Inter-chip Proximity Communication and worked on Si nano-photonics solutions for data communications within computers. Before joining Sun Microsystems he served as the chief scientist at Aralight where he developed products based on the hybrid integration of Vertical Cavity Surface Emitting Lasers and photodetectors with CMOS, a technology he co-developed at Bell Laboratories. While at Bell Laboratories he also pioneered eight world records on various types of quantum mechanically engineered devices and materials and co-authored over 360 journal papers including some with Nobel Prize Laureates, as well as 40 U.S. patents.

Before joining Bell Laboratories has was a member of the research faculty in the Physics Department at the University of Illinois where he initiated the first Metals Molecular Beam Epitaxy. He received his PhD and MS in physics from University of Illinois at Champaign-Urbana and a BS in physics, University of Tennessee at Knoxville. John is currently a distinguished engineer at Sun Labs of Oracle and is the principal lead of the Advanced Packaging Group while simultaneously serving as the co-principal investigator of the DARPA UNIC project.

Denis Dutoit
Research Engineer
CEA-Leti

Denis Dutoit joined CEA-Leti as a research engineer in 2009, after working for STMicroelectronics and then ST-Ericsson where he has held several positions from digital circuit designer to digital SoC architecture manager. In CEA-Leti, he is currently involved in system-on-chip architecture and 3-D integrated circuit projects; he has been the lead architect of a Wide IO capable MP-SoC design. Denis holds an engineering degree from the École Nationale Supérieure d'Électronique et de Radioélectricité de Grenoble, and a PhD in signal processing from the École Nationale Supérieure des Télécommunications de Paris. He is a co-recipient of the Jan Van Vessem Award for Outstanding European Paper at ISSCC 2005.

Ron Huemoeller
Senior Vice President, Advanced Product Platform Development
Amkor Technology

Ron has more than 25 years of experience in the semiconductor industry in advanced product development. Currently, as senior vice president of advanced interconnect platform development at Amkor Technology, he is responsible for corporate strategy, business development, and deployment from feasibility into production of advanced technology platforms, including TSV. Prior to Amkor, Ron was director of engineering at Cray Computer Corporation in Colorado Springs, leading the development of state of the art motherboards for the world's fastest super computer. He has authored numerous technical publications, co-authored the chapter on "Assembly and Test Aspects of TSV Technology" in the Handbook of 3D Stacking, and has been granted 61 U.S. patents. Ron holds a BS in chemistry from Augsburg College with highest honors, an MBA from Arizona State University, and a master's in technology management from the University of Phoenix.

Georg Kimmich
Technology Manager
ST Ericsson

Georg Kimmich is technology manager at ST-Ericsson in Grenoble, France. His focus is on the package technology roadmap definition for smartphone and tablet chip sets.

Previously Georg Kimmich held several R&D and R&D management positions in the design automation and system on chip design domain with Thomson Multimedia, STMicroelectronics, and ST-Ericsson in Germany, France, and the U.S.

Dim-Lee Kwong
Executive Director
Institute of Microelectronics

Dim-Lee Kwong is the executive director of Institute of Microelectronics (IME), Agency for Science, Technology and Research (A*STAR), Singapore, a professor of electrical and computer engineering at National University of Singapore, and an adjunct professor of electrical and computer engineering at the University of Texas at Austin. He was Earl N. and Margaret Bransfield Endowed Professor at the University of Texas at Austin from 1990-2007, and the Temasek Professor of National University of Singapore from 2001-2004.

Dim-Lee received the IBM Faculty Award in 1984-86, Semiconductor Research Corporation (SRC) Inventor Awards in 1993-94, General Motor Foundation Fellowship in 1992-95, Halliburton Foundation Excellent Teaching Award in 1994, Engineering Foundation Award in 1995, IEEE George Smith Award in 2007, and the 2011 IEEE Frederik Philips Award with citation: "For leadership in silicon technology and excellence in the management of microelectronics R&D." He is an IEEE Fellow.

Dim-Lee is the author of more than 1100 referred archival publications (600 journal and 500 conference proceedings), has presented more than 80 plenary and invited talks at international conferences, and has been awarded with more than 25 U.S. patents. He was the founder of Rapro Technology in 1986 and Micro Integration Corporation in 1988, and has been consultant to government research labs, semiconductor IC manufacturers, and materials and equipment suppliers in U.S. and overseas.

John Lannon
Sr. Research Engineer
RTI International

John Lannon is a senior research engineer and manager of the Microsystem Integration and Packaging group at RTI International. He has over 15 years of professional experience in semiconductor device processing technology, thin film processing and characterization, and process integration. John has been involved in the development of metal-metal bonding schemes for high density interconnect bonding applications (e.g., imaging and sensor devices) and hermetic seal bonding. For the past 10 years, he has also been involved in the process transfer, management, monolithic fabrication, and further development of resistive IR scene projector devices, a microbolometer-like device technology originally developed at Honeywell. John has a PhD in solid state physics from West Virginia University where he performed research on the growth and characterization of diamond thin films for electronic applications. He has authored or co-authored over 25 publications and holds one U.S. patent.

Yusuf Leblebici
Professor
Swiss Federal Institute of Technology

Yusuf Leblebici received his BSc and MSc degrees in electrical engineering from Istanbul Technical University, Istanbul, Turkey, and his PhD degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign. Between 1991 and 2001, he worked as a faculty member at UIUC, at Istanbul Technical University, and at Worcester Polytechnic Institute (WPI). In 2000-2001, he also served as the Microelectronics Program Coordinator at Sabanci University.

Since 2002, Yusuf has been a chair professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), and director of Microelectronic Systems Laboratory. His research interests include design of high-speed CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, intelligent sensor interfaces, modeling and simulation of semiconductor devices, and VLSI reliability analysis. Since 2002, Yusuf has been a chair professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), and director of Microelectronic Systems Laboratory. His research interests include design of high-speed CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, intelligent sensor interfaces, modeling and simulation of semiconductor devices, and VLSI reliability analysis.

Yusuf is the coauthor of four textbooks, namely, Hot-Carrier Reliability of MOS VLSI Circuits, CMOS Digital Integrated Circuits: Analysis and Design, CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications, and Fundamentals of High Frequency CMOS Analog Integrated Circuits, as well as more than 200 articles published in various journals and conferences.

Yusuf has served as an associate editor of IEEE Transactions on Circuits and Systems (II) and IEEE Transactions on Very Large Scale Integration (vlsi) Systems. He has also served as the general co-chair of the 2006 European Solid-State Circuits Conference, and the 2006 European Solid State Device Research Conference (ESSCIRC/ESSDERC). He is a Fellow of IEEE since 2010, and he has been elected as Distinguished Lecturer of the IEEE Circuits and Systems Society for 2010-2011.

Patrick Leduc
3-D IC Program Manager
CEA-Leti

Patrick Leduc is program manager of 3-D IC activities in CEA-Leti. He received his MSc degree in solid-state physics from the Polytechnics Institute of Grenoble in 1998 and joined the CEA-LETI in 2000. His field of expertise is advanced technologies for 3-D integration. During his career in semiconductor, he was involved in process development (chemical mechanical planarization) for CMOS devices, in the integration of on-chip interconnects, and, since 2006, he has been in charge of several 3-D integration projects for CMOS applications. Since 2012, his current position is 3-D IC program manager.

Erik Jan Marinissen
Principal Scientist
IMEC

Erik Jan Marinissen is principal scientist at IMEC in Leuven, Belgium. Previously, he worked at NXP Semiconductors and Philips Research, both in Eindhoven, The Netherlands. Marinissen holds an MSc degree in computing science and a PDEng degree in software technology, both from Eindhoven University of Technology.

Erik’s research interests include all topics in the domain of test and debug of micro-electronics. He is co-author of over 170 journal and conference papers and co-inventor on nine granted U.S. and EP patent families. He is the recipient of the ITC 2008 and ITC 2010 Most Significant Paper Awards and Best Paper Awards at the Chrysler-Delco-Ford Automotive Electronics Reliability Workshop 1995 and the IEEE International Board Test Workshop 2002. He served as editor-in-chief of IEEE Std 1500 and founded and chairs the IEEE P1838 Working Group on standardization of a 3-D test access architecture. He is a founder of workshops on Diagnostic Services in Network-on-Chips, 3-D Integration, and Testing of Three-Dimensional Stacked Integrated Circuits. He serves on numerous conference committees, including ATS, DATE, ETS, ITC, and VTS, and on the editorial boards of IEEE Design & Test of Computers, IET Computers and Digital Techniques, and Springer’s Journal of Electronic Testing: Theory and Applications (JETTA). Erik is a Fellow of IEEE and Golden Core Member of Computer Society.

Thorsten Matthias
Director of Business Development
EV Group

Thorsten Matthias is director of business development at EV Group headquarters in St. Florian, Austria. In this role he is responsible for overseeing EVG's worldwide business development. Thorsten received his PhD in Technical Physics in 2002 from Vienna University of Technology. He started working at EV Group in October 2002. In his current position he works in 3-D integration, MEMS, photovoltaics, LED, and nanotechnology. Since 2002 he has been involved in the field of 3-D integration. He has contributed chapters to three books on TSV and 3-D integration and authored multiple papers with a special focus on thin wafer handling and chip stacking.

Lisa McIlrath
President, CEO
R3Logic

Lisa McIlrath has over 22 years of experience in solid-state circuit design, of which the last 16 have been in developing 3-D systems architectures and EDA tools. She was the designer of one of the world's first fully functional 3-D integrated circuits fabricated in 1998. Lisa founded R3Logic in 2000 with the mission of developing design tools for the newly emerging field of 3-D integration. Over the years R3Logic has worked with major IDMs as well as with U.S. DoD agencies on numerous 3-D design projects and holds several key patents on 3-D EDA systems and methods. Lisa received a PhD in electrical engineering and computer science from MIT in 1994, an MS in operations research from the University of Texas at Austin in 1989, and a BS in physics from MIT in 1976. From 1994 to 1998 she was an assistant professor of electrical and computer engineering at Northeastern University; and, from 1998 through September 2000, a visiting professor at the MIT Artificial Intelligence Lab

Robert Patti
CTO, Vice President of Design Engineering
Tezzaron Semiconductor

Bob Patti attended Rose-Hulman Institute of Technology, earning bachelor of science degrees in both physics and electrical engineering. He founded an R&D company specializing in high-performance systems and ASICs and participated in the design of over 100 chips in the course of 12 years. Tezzaron Semiconductor grew from that company to become a leading force in 3-D IC technology, building its first working 3-D ICs in 2004. Today Bob is the CTO of Tezzaron, using wafer-level stacking processes to create ultra high-density 3-D memory products and other semiconductor sub-components. He received the SEMI Award for North America in 2009, served as vice-chairman of JEDEC's DDRIII / Future Memories Task Group, and holds 17 U.S. patents, numerous foreign patents, and many more pending patent applications in deep sub-micron semiconductor chip technologies.

Bassilios Petrakis
Cadence Design Systems

Riko Radojcic
Director
Qualcomm

Riko Radojcic is a director of engineering at Qualcomm CDMA Technologies, and a leader of various design-for-technology initiatives; including Design-for-3-D, Design-for-Thermal, Design-for-Manufacturability & Variability, Si-Package CoDesign, etc., and involving methodologies at polygon, circuit, logic, and/or system design levels.

Riko has more than 30years experience in the semiconductor industry, specializing in the integration of process, design and EDA considerations, and design-for-Si solutions. Before joining Qualcomm, he was a consultant to semiconductor and EDA companies providing engineering and business development services focused on process-design integration. He was a director of business development and marketing for DFM Solutions at PDF Solutions, and a business manager and an architect with Tality and Cadence, specializing in design technology integration and process characterization and modeling.

Riko has held a series of managerial and engineering positions with Unisys and Burroughs in device engineering, failure analyses, and reliability engineering areas. He began his career as a process engineer with Ferranti Electronics, UK. He received his BSc and PhD degrees from University of Salford, UK.

Arifur Rahman
Product Architect
Altera Corporation

Arif Rahman is an architect at Altera and manages the product architecture. He has more than 15 years of research and product development experience in circuits and architecture, design methodology, manufacturing technology, and supply chain strategy. Prior to Altera, he worked at Xilinx, Agere Systems, Lattice Semiconductor, and Polytechnic University, NY. Arif holds a PhD degree from MIT in electrical engineering and an MBA from Santa Clara University. He has authored numerous articles and has been granted 50 patents. He serves in the program committee of IEEE Custom Integrated Circuits Conference.

Sesh Ramaswami
Managing Director
Applied Materials

Sesh Ramaswami is managing director, Wafer Level Packaging Technology in the Silicon Systems Group at Applied Materials. His responsibilities span roadmap development, technology assessment and validation, business strategy, and industry collaborations within the context of wafer level processing for advanced chip-chip and chip-substrate packaging interconnects. He is a co-author and contributor of a book recently published by McGraw Hill, entitled 3-D IC Stacking Technology.

Sesh has over 25 years of semiconductor industry experience, with the last 17 at Applied Materials in various technical and business functions. Prior to Applied Materials, Sesh had process development responsibilities at Advanced Micro Devices and National Semiconductor. A holder of thirty-five U.S. patents, Sesh has undergraduate and graduate degrees in chemical engineering from Indian Institute of Technology, Kanpur, and Syracuse University, respectively, and an MBA.

Daniel Rishavy
Product Manager
Tokyo Electron America

Dan is the marketing and applications manager for Tokyo Electron America's Test Systems group. He holds a BSEE degree from the University of South Florida and has been working in the Semiconductor Test industry for 15 years. He has held Variety of roles throughout his career at Hewlett Packard, Agilent, Verigy and now TEL.

Chris Sanders
Director Business Development
Ziptronix

Chris Sanders serves as director of business development at Ziptronix, responsible for commercializing their significant patent portfolio in low temperature direct bonding primarily through licensing. He is also responsible for developing high-level strategic relationships with a wide range of companies all over the world, which have interest in creating value for their organizations in 3-D integration coupled with the utilization of Ziptronix’s proven technology.

Chris has over 20 years of engineering, business development, management and licensing experience in Europe, Asia, and the U.S. with most of his work focused in advanced semiconductor and medical device technologies. Chris holds a BS in Aerospace Engineering from North Carolina State University and is a member of the Licensing Executive Society.

Steve Smith
Senior Director of Marketing, 3-D IC
Synopsys

Steve Smith is currently responsible for Synopsys' 3-D IC strategy and marketing. He has been with Synopsys for 15 years, having served in various functional verification and design implementation marketing roles. He has worked in the electronic design automation and computer industries for more than 30 years in a variety of senior positions including marketing, applications engineering, and software development. Prior to Synopsys, Steve worked at Viewlogic, CrossCheck, Teradyne, Unisys, and ICL. Steve holds a bachelor's degree in statistics and numerical analysis from Lancaster University, England.

Jan Vardaman
President
TechSearch International

E. Jan Vardaman is president and founder of TechSearch International, which has provided licensing and consulting services in semiconductor packaging since 1987. She is the co-author of How to Make IC Packages, a columnist with Circuits Assembly/Printed Circuit Board Fabrication, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a member of IEEE CPMT, SMTA, MEPTEC, IPC, IMAPS and SEMI. She was elected to two terms on the IEEE CPMT Board of Governors. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry's first pre-competitive research consortium. Jan has made numerous presentations and organized panel discussions on 3-D TSV.

M. Juergen Wolf
Fraunhofer IZM-ASSID

In 1994, M. Juergen joined Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin and has worked as group & project manager in the field of wafer level packaging and system in package (SiP). Since 2011 he has been the head of department HDI&WLP/ASSID, responsible for the coordination and management of ASSID (All Silicon System Integration Dresden-ASSID) with its 300 mm Wafer Level Integration. He manages as well as participates in a number of research projects on an international level. M. Juergen is a European representative in the technical working group Assembly & Packaging of ITRS, JEC, JIC and a board member of EURIPIDES, as well as a member of IEEE and SMTA. He has authored and co-authored numerous scientific papers and reports in the field of microelectronic packaging and holds a number of patents.

M. Juergen holds an MS degree in electrical engineering.

Daquan Yu
Professor
Chinese Academy of Sciences – Institute of Microelectronics

Daquan Yu received his BA and PhD degrees from Dalian University of Technology, P. R. China. He has worked at Fraunhofer IZM in Berlin, Germany and Institute of Microelectronics in Singapore. Since 2010, he has been a professor of Institute of Microelectronics, Chinese Academy of Sciences. Currently, he is the deputy director of system packaging lab and leads a research group working on 3-D TSV integration. He is an adjunct Fellow researcher at University of Science and Technology of China. He is also the head of system packaging lab in the Jiangsu R&D Center for Internet of Things. In 2011, he promoted the foundation of China TSV Consortium and worked with local companies and institutes on TSV interposer technology. So far, he has authored or co-authored more than 80 peer-reviewed technical publications and has about 20 issued and pending patents.